1. Field of the Invention
The present invention relates to a semiconductor memory apparatus and in particular to a semiconductor memory apparatus comprising a timing control circuit simulating a signal delay.
2. Description of the Related Art
In a semiconductor memory apparatus, an activation timing for a sense amplifier amplifying a data read out of a memory cell is designed to occur after a voltage difference between a bit-line pair becomes amply apart.
An activation signal controlling the activation timing for a sense amplifier is preferable to be generated at the shortest timing after a predefined voltage is generated between a bit-line pair, thereby shortening an access time.
However, while the capability of driving the bit-line of a memory cell depends on the electrical characteristics of transistors therein which vary in the manufacturing process thereof, therefore the activation signal generation needs to have an ample timing margin. And the timing margin causes a problem of an access time to a memory becoming longer.
A method for solving the problem is to equip a dummy circuit made up of a word-line, memory cells and a bit-line, and to generate an activating signal for a sense amplifier by utilizing a self-timing circuit which simulates a signal delay within a semiconductor memory apparatus by using the dummy circuit.
FIG. 1 illustrates a summary framework of a semiconductor memory apparatus having a setup for a self-timing. FIG. 1 shows only a part thereof related to a data read-out.
In FIG. 1, a semiconductor memory apparatus comprises a main decoder 11 decoding an externally supplied address signal, generating a word-line selection signal and selecting one memory cell from among a cell array 13; a self-timing circuit 12 generating timing control signals such as a sense amplifier starting signal; a cell array 13 comprising a plurality of memory cells; a clock pulse generation circuit 14 generating a base clock signal and a column selection signal by decoding an address selection signal; a column switch and sense amplifier 15 including a column switch for selecting a bit-line of a memory array by a column selection signal from the clock pulse generation circuit 14 and a sense amplifier for amplifying an output from the column switch; and an input-output circuit 16 outputting a read-out output from the sense amplifier to the outside as a data.
The self-timing circuit 12 generates an activation signal for controlling activation timing for the sense amplifier from a clock signal inputted by the clock pulse generation circuit 14, and inputs the signal to the sense amplifier 15.
The self-timing circuit 12 comprises a dummy word line 24, and a dummy bit-line 25 comprising a charge extraction dummy cell 22 and a load dummy cell 23. And, when the dummy word-line 24 is driven by a signal which is a clock signal outputted from the clock pulse generation circuit 14 and then amplified by an inverter 21 so that the charge extraction dummy cell 22 is selected, then the dummy bit line 25 is driven. The signal on the dummy bit line 25 is then amplified by the buffers 26 and 27, and thereby an activation signal is generated for controlling timing of the sense amplifier activation.
Meanwhile, as a method for generating an activation signal for a sense amplifier by using a dummy cell as described above, known is a configuration which comprises a plurality of bit-lines having a different number of dummy cells and adjusts a delay time length by selecting one of the aforementioned dummy bit-lines as a pre-adjustment, as presented by the patent document 1 (i.e., a Japanese patent laid-open application publication 2002-216481; FIG. 4 and paragraphs 0019 to 0020).
Since a memory array is large in physical size, a distance from a memory cell to the sense amplifier varies in great deal depending on the location of a memory cell in a memory array, and accordingly a magnitude of the signal delay. Therefore a semiconductor memory apparatus equipped with a common self-timing circuit having only one dummy bit-line (i.e., a pair thereof) is not capable of precisely simulating the signal delays for the memory cells in all the locations.
Also in a configuration having a plurality of dummy bit-lines as presented by the patent document 1 noted above, et cetera, switching a dummy bit-line is set up as a transmission gate, not a column switch used in the normal path for reading data out of non-dummy cells. This makes the magnitude of signal delay through the dummy bit-line path in the simulation different from the actual path for reading data out of a memory cell.
Furthermore, in the configuration as presented by the patent document 1 above, et cetera, a plurality of dummy bit-lines are subjected to switching which is not done dynamically during the normal operation reading data out of the semiconductor memory apparatus, but is done by a method such as using an input value from an external terminal for setting a state, or cutting off a fuse, in order to go through an adjustment after the initial evaluation. Therefore, it is not possible to switch dynamically a dummy bit-line to be used. On the contrary, for example, it is required to set a larger delay for reading data out of a memory cell in longer distance from the column switch while a smaller delay for reading out thereof in shorter distance therefrom, thus precluding a dynamic switching of a plurality of dummy bit-lines in actual operations.